Checked before it ships

A board is ready to fabricate when every gate passes on the exact revision you order. Each finding says how it is known.

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The gates

  1. Electrical rules

    Each pin's role from the part's library symbol or its datasheet: unpowered supply pins, floating grounds, must-connect pins left open, do-not-connect pins used, driven outputs in conflict, open-drain lines without pull-ups, one decoupling capacitor per IC supply pin, LED current.

    Measured on the netlist, calculated from part values

  2. Schematic

    tscircuit's schematic checks on the drawn sheet: text over parts, overlapping symbols and labels, two-pin parts drawn the wrong way round.

    Measured on the drawing

  3. Simulation

    An ngspice DC operating point of the whole board, and a power budget per load scenario: rail droop, regulator dropout, overload and regulator heat, inrush at the source. Experiments the board declares run as transient analyses with their probes plotted.

    Simulated in ngspice

  4. Boot & pins

    Will the microcontroller start: boot and strapping pins at their simulated voltages, flash, PSRAM and input-only pins, debug pins and pin functions, against the maker's rules for RP2040/RP2350, STM32, ESP32, nRF52 and AVR.

    Simulated voltages against datasheet rules

  5. Layout & DRC

    tscircuit's DRC on the routed copper of the exact source revision: clearances, shorts, unrouted connections, overlapping parts. A route made for an older revision never counts.

    Measured on the copper

  6. Signal & power

    Differential pair impedance from a 2D field solver on the fab's stackup, each pair's edge simulated at its receiver with the common-mode noise its skew makes, crosstalk as the voltage a fast edge puts on its neighbour, return paths, bus timing against each interface's bit time (QSPI, SDIO, RMII, RGMII), trace current against IPC-2221, DC drop on rail and ground copper, supply impedance across frequency against each rail's load step, board, junction and in-enclosure temperature, and each fast edge simulated in ngspice with the maker's IBIS model, found by part number where the maker publishes it.

    Solved on the routed geometry; checked against Elmer FEM, ngspice and closed-form results

  7. Manufacturability

    The board's measured minimums against JLCPCB, PCBWay and OSH Park standard capabilities (trace spacing, drills, annular rings, hole to copper, copper to edge, silkscreen), SMD pad spacing between nets, Gerber and drill completeness, each part's pads against JLCPCB's own footprint for pinout and pick-and-place rotation, polarity marks read from the silkscreen's geometry, tombstoning risk on small parts, fiducials, and a probe point on every rail for bring-up.

    Measured on the fabrication files

  8. Parts & supply

    Every part has an orderable LCSC number, stock for the build quantity and the package the footprint expects, looked up live.

    Sourced from JLCPCB at check time

  9. Mechanical fit

    Board outline, mounting holes, part heights and connectors at a reachable edge. Enclosures and brackets the agent models are checked against the board: valid solids, no clash with the board or any part, every connector and control open to the outside, parts of an assembly clear of each other.

    Measured on the 3D board and the CAD solids

Not yet: full-wave S-parameters (USB 3, PCIe, DDR4 channels) and radiated emissions. For those, export and finish in a field solver.

How a verdict is made

  1. Evidence, not claims

    Every finding is labelled measured, simulated, calculated, sourced or declared, so a simulated voltage is never read as a bench measurement.

  2. No silent passes

    A check that cannot run (no routed copper, no power model, a parts service out of reach) says why, and its gate reads not run instead of passing.

  3. One revision

    Routing and checks belong to the source revision they ran on. Change the circuit and the old route and its results no longer count.

  4. The agent answers to it

    The agent calls the same report and fixes what it finds. It may say a board is ready only when the report does.

Questions

Is fluxboards for hobbyists or for professional boards?
Both, with the same checks. Starting takes no install, no EDA training and, for a first board, no sign-up. What decides a board is ready is the same for everyone: field-solved differential impedance, return paths and crosstalk, IPC-2221 trace current, DC drop and board temperature on the routed copper, and its measured minimums against JLCPCB, PCBWay and OSH Park. Every finding says how it is known (measured, simulated, calculated or sourced), and a check that could not run says why instead of passing. Bring a board you know well to fluxboards.tech/bench and compare.
What fabrication checks does fluxboards run before export?
Readiness gates on the exact revision: electrical rules, schematic, simulation, boot & pins, layout & drc, signal & power, manufacturability, parts & supply, mechanical fit. A board is called ready to fabricate only when the report says so, never on the model's word. Every check is listed at fluxboards.tech/readiness.
Does fluxboards handle high-speed and controlled-impedance boards?
It checks what a routed board can show: differential pair impedance from a 2D field solver on JLCPCB's stackups; each pair's edge simulated at its receiver as coupled lines, with the common-mode noise its skew makes; crosstalk as the millivolts a fast edge puts on its neighbour, at both of its ends; bus skew against the bit time of QSPI, SDIO, RMII and RGMII; an unbroken reference plane and return path under fast nets; each rail's supply impedance across frequency against its load step; and each fast edge simulated with the maker's IBIS model, fetched by part number where the maker allows it. Not yet: full-wave S-parameters (USB 3, PCIe, DDR4 channels) and radiated emissions. For those, export and finish in a field solver.